1. Field of the Invention
The present invention relates to an interface circuit using a reference voltage.
2. Description of the Related Art
A conventional stub series terminated logic (SSTL) interface circuit for interfacing between a memory controller and a memory can be configured as illustrated in FIG. 1.
In the SSTL interface circuit illustrated in FIG. 1, a memory 101 is controlled by a memory controller 102. Both the memory 101 and the memory controller 102 are connected to a reference voltage generation circuit 103. The same power VDDQ and reference voltage VREF are input to the memory 101 and the memory controller 102. In this configuration, the memory controller 102 cannot be separately powered off while electric power is being supplied to the memory 101. VTT represents termination voltage. Accordingly, when the memory 101 is backed up, the memory controller 102 wastes supplied electric power.
As a method for solving this problem, there is a configuration as illustrated in FIG. 2, in which two separate powers VDDQ1 and VDDQ2 are supplied to a memory 201 and a memory controller 202, respectively, and reference voltage generation circuits 203 and 204 are coupled to the memory 201 and the memory controller 202, respectively. This configuration enables the memory 201 to be backed up by turning off the power VDDQ2 and VTT to the memory controller 202 while supplying the power VDDQ1 to the memory 201.
Further, Japanese Patent Application Laid-Open No. 2002-7309 discusses an SSTL interface circuit in which two separate power supplies are respectively provided for a memory and a memory controller, and a channel line that connects the memory and the memory controller responds to a termination voltage, which is independent of power supply voltages to the memory and the memory controller.
However, in the above-described conventional example, separate powers are respectively supplied to the memory 201 and the memory controller 202. This causes a difference in power supply voltage, thus causing a difference in output voltage between the reference voltage generation circuits 203 and 204.
The SSTL interface circuit can reduce the amplitude of a signal to increase a transfer rate. For example, a reference voltage for use in a double-data-rate synchronous dynamic random access memory (DDR SDRAM) interface circuit requires an accuracy of ±2%. Accordingly, when the DDR SDRAM interface circuit receives two separate powers, it is necessary to decrease a difference in power supply voltage to within ±2%. If the DDR SDRAM interface circuit does not satisfy the accuracy of the reference voltage, the timing margin of setup hold time of a signal line is reduced. Accordingly, even if the DDR SDRAM interface circuit can receive two separate powers, it is difficult to increase the transfer rate of the DDR SDRAM interface circuit.
Further, as illustrated in FIG. 3, a common power VDDQ1 can be used to activate a memory 301 and a memory controller 302, and a power disconnect circuit 306 can turn off power to the memory controller 302. Reference voltage generation circuits 303 and 304 function similar to voltage generation circuits 203 and 204 from FIG. 2. This configuration can improve the accuracy of a reference voltage to some extent as compared with the configuration in FIG. 2. However, the power disconnect circuit 306 is generally configured with a field-effect transistor (FET). Since such a power disconnect circuit 306 generates an on-resistance, an input and output voltage drops by an amount of “on-resistance”×“electric current consumption”. If the electric current consumption is large, the accuracy of a reference voltage is not satisfied. Further, in order to reduce the on-resistance, a plurality of FETs are required, thus resulting in high production cost.
As another method, if an SSTL interface circuit increases the output electric current capacity of an output buffer, the timing margin can be improved. However, if the SSTL interface circuit increases the output electric current capacity of the output buffer, a capacitor needs to be strengthened and the number of powers and grounding (GND) pins for a memory controller needs to be increased to stabilize a power supply circuit. This configuration may result in increasing cost. Further, the timing margin can be improved only to an extent that it is still reduced compared to when the accuracy of a reference voltage is satisfied.